The present invention relates to a pipeline circuit for adjusting the data timing in a data processing system.
Usually, a timing-adjusting pipeline circuit is used for adjusting the timing of data transfers between processing units, particularly for adjusting the timing of data transfers to an interleave type processing unit from another processing unit.
An interleave type processing unit in this context typically is a memory unit consisting of a plurality of banks which are used in a time-share manner. Another example of interleave type processing unit is an arithmetic system comprising a plurality of low-speed arithmetic units which are used in a time-share manner to let the whole system achieve high-speed arithmetic operation.
In an actual data processing system, in order that data, which is to be written into memory, match the interleave timing as input data to an interleave type processing unit, some kind of timing adjustment is required.
A conceivable method of timing adjustment is to adjust the actuating timing of a data processing instruction so that the processed data reach the input crossbar at the interleave timing referred to above. This method necessitates no particular timing adjuster. However, it entails complex control of the instruction actuating timing, and thereby affects the processing start times of processing units other than the memory and may deteriorate the overall performance of the data processing system.
Therefore, a timing-adjusting circuit should be provided immediately before the input crossbar.
If a serial data A=(a.sub.1, a.sub.2, . . . , a.sub.m) are inputted, the output timing of the first datum a is adjusted with a selection signal S. The output timing of the succeeding data a.sub.2, a.sub.3, . . . (inputs to the interleave type processing unit) are controlled so as to be identical with the interleave timing by maintaining the selection signal S at the time the datum a: is outputted. Such a circuit cannot be used when, for instance, the input timings of different data are irregular, as is the case with the output data of a processing unit whose processing time differs with the value of each datum. Also, such a circuit cannot be used when the series of data include invalid ones that cannot be processed with an interleave type processing unit, such as data for masked vector processing.